1. Field of the Invention
The invention relates generally to a nonvolatile semiconductor storage device having a memory array configured such that a plurality of nonvolatile semiconductor memory cells capable of storing one-bit information or multi-bit information are individually arranged in a row direction and a column direction. The memory array has a plurality of row lines and a plurality of column lines that are arranged to enable selection of a predetermined memory cell or memory cells from the plurality of memory cells. More specifically, the invention relates to a nonvolatile semiconductor storage device having a row-line short detection function and to a row-line short defect detection method for detecting a row-line short defect in a nonvolatile semiconductor storage device.
2. Description of the Related Art
With recent rapid advances in the development of semiconductor integrated circuit technology, also in the field of nonvolatile semiconductor storage devices, the storage capacities thereof are increased through miniaturization and compact integration of memory cells. In line with the technological advancement, design rules for components, such as transistors and wires, to be used with the devices are made to be correspondingly fine. Conventionally, in the field of nonvolatile semiconductor storage devices, measurement is carried out to test row-line short defects, which is one type of memory cell defects. The types of such measurement include “leaky-row measurement” (which is performed to test the presence or absence of leakage between adjacent row lines).
The leaky-row measurement will be described hereunder with reference to a conventional example shown FIG. 4. FIG. 4 depicts a conventional example a nonvolatile semiconductor storage device having a row-line short defect detection function.
Referring to FIG. 4, the nonvolatile semiconductor storage device has a memory array 1, a row decoder 2, a column decoder 3, a common source line driver 4, a mode switch circuit 5, a booster circuit 6, and an external connecting pad 7 that receives a testing voltage supplied from a testing voltage source. In addition, similar to a general-purpose semiconductor memory, the nonvolatile semiconductor storage device has peripheral circuits, such as an address input circuit, data input/output circuit, and a control signal input circuit. However, since the peripheral circuits are not directly related to explanation of the leaky-row measurement, the circuits are not shown in the drawing.
The configuration of the memory cell array 1 will be described hereunder. Memory cells, each of which is formed of a single floating gate MOSFET, for example, are arranged in the vertical and transverse directions in the form of an array. In the array, a plurality of row lines WL and a plurality of column lines BL are individually arranged in the transverse direction (row direction) and the vertical direction (column direction) to be used for selection of a predetermined memory cell or memory cells from the overall memory cells. Referring to FIG. 4, the plurality of row lines WL consist of n+1 row lines WL0 to WLn (“n” represents a non-negative integer) and are connected to control gates of individual memory cell transistors in the transverse direction (row direction), thereby enabling application of a predetermined voltage. In addition, in the configuration shown in FIG. 4, the plurality of column lines BL consist of m+1 column lines BL0 to BLm (“m” represents a non-negative integer) and are connected to the drains of the individual memory cell transistors, thereby enabling data transfer (such as reads or programs of data) from or to the individual memory cells. The sources of the individual memory cell transistors are commonly used, and hence the sources are connected to a common source line CS.
The row decoder 2 is formed to be capable of selecting at least one of the plurality of row lines WL0 to WLn and selectively setting the selected lines to a voltage level different from that set for others not selected. Row drivers 0 to n are connected to the individual row lines WL0 to WLn to individually function as row-line select circuits that supply drive voltages to the individual row lines WL0 to WLn. In the individual row drivers 0 to n, row predecoders are provided that individually decode input signals into selection/non-selection signals in accordance with address signals (not shown). The row drivers 0 to n and the row predecoders each cooperatively form a rearstage section 2a and a forestage section 2b. 
In a flash memory, which is a typical or representative nonvolatile semiconductor storage device, a high voltage of 9V, for example, is applied thereto in a row-line selection mode for an operation such as a program (program operation). In the conventional example case, the booster circuit 6 (charge pump circuit) is built in the nonvolatile semiconductor storage device to cause intradevice charge pumping for a power supply voltage (of 3V or 5V, for example) of the storage device. A row driver i (i=any one of 0 to n) has a double-stage configuration with a driver stage (formed of transistors MPi2 and MNi2) and a predriver stage (formed of transistors MPi1 and MNi1). The former driver stage is used as a driver circuit that applies 9V to a row line WLi in a selection mode and that applies 0V to the row line WLi in the unselected state. The latter predriver stage drives the driver stage to accelerate access (to increase the selection/non-selection switching speed).
The column decoder 3 is connected to the individual column lines BL0 to BLm. The column decoder 3 includes, for example, a driver and a sense amplifier. The drive is used to apply predetermined voltages to the individual column lines BL0 to BLm in individual program and erase modes. The sense amplifier is used to detect the potentials of all or a selected number of column lines at a read mode. The common source line driver 4 is configured of a driver that applies predetermined voltages to the common source line CS in the individual program, erase, and read modes.
The mode switch circuit 5 is responsible to switch between two modes of applying voltages to a row driver selected by the corresponding row predecoder. One mode is to apply the selected row driver with a voltage that is output from the booster circuit 6 in a normal operation mode. The other mode is to apply the selected row driver with a testing voltage (Vpp) that is output from the external connecting pad 7 in a test mode. In the example configuration shown in FIG. 4, the mode switch circuit 5 is configured of three types of input selection circuits 8a to 8c, each of which is of a two-input/one-output type. The input selection circuits 8a to 8c are each configured of a pair of switching devices. In this configuration, a voltage applied by a mode switch signal to one of the two input terminals is supplied to the output terminal. In addition, in the configuration, the voltage to be applied to the two input terminals can be divided to supply an intermediate voltage to the output terminal.
The first input selection circuit 8a is responsible to switch the supply source of a voltage Vpix (the well (backgate) voltage of the transistor MPi2 of the row driver, and a well (backgate) voltage of the transistor MPi1) between the normal operation mode and the test mode. The second input selection circuit 8b is responsible to switch the supply source of a voltage Vpx (the source voltage of the transistor MPi2 of the row driver) between the normal operation mode and the test mode. The third input selection circuit 8c is responsible to switch the supply source of a voltage Vpg (the gate voltage of the transistor MPi1) between the normal operation mode and the test mode. However, the third input selection circuit 8c does not perform the simple operation of switching the voltage supply source between the normal operation mode and the test mode, but also performs the following operations. In the normal operation mode, the circuit 8c sets both the switching devices to the conductive state to enable the transistor MPi1 to be concurrently used as a pullup resistant component. Where, the voltage Vpg, which is lower than the voltage Vpx, is generated through resistance-type potential division, and the transistor MPi1 is driven to the on-state to boost an output node DGi of the predriver stage to the high voltage of 9V through the pullup resistant component. In the test mode, the circuit 8c fixes the voltage Vpg to the ground potential.
The individual switching devices of the individual input selection circuits 8a to 8c are operated as described hereunder. In the normal operation mode, switching devices SW1, SW3, SW5, and SW6 are set to the conductive state, and switching devices SW2 and SW4 are set to the nonconductive state. In the test mode, the switching devices SW2, SW4, and SW6 are set to the conductive state, and the switching devices SW1, SW3, and SW5 are set to the nonconductive state.
A detection method for the presence or absence of leakage current between adjacent row lines will be described hereinbelow. In this method, a leakage current detected between adjacent row lines indicates occurrence of a short defect. In the test mode, the common source line CS and the individual column lines BL0 to BLm are grounded. Then, as described above, the mode switch circuit 5 sets the switching devices SW2, SW4, and SW6 to the conductive state, and sets the switching devices SW1, SW3, and SW5 to the nonconductive state. FIG. 2 shows a case where one row line (WL0) is selected from all the row lines WL0 to WLn of the memory array 1, and the test voltage Vpp (9V, for example) is applied from the external connecting pad 7. In this case, the method measures a current (Ipp) flowing through the pad 7. Then, the method sequentially selects the row lines, and measures the individual currents Ipp flowing through the external connecting pad 7. During the measurement, suppose that an inter-row-line short defect is detected at the portion between a node A on the row line WL0 and a node B on the row line WL1, shown in FIG. 4. In this case, a current path is formed from the external connecting pad 7 to Vss (ground potential) via the switching device SW4, transistors MP02, row lines WL0 and WL1, and transistor MN12, and a leakage current flows through the current path. As such, the portion of inter-row-line short defect can be detected by detection of the current Ipp.
However, since each of the transistors MP02 and MN01 of the predriver stage in the row driver corresponding to the selected row line is in the on-state in which a pass-through current is kept flowing therethrough, the measured current Ipp usually contains the component of the pass-through current as a bias current. That is, since the current Ipp is detected regardless of the presence or absence of an inter-row-line short defect, the method needs to determine the presence or absence of a short defect by measuring the value of current. Additionally, the pass-through current varies depending on factors such as the manufacturing condition and measuring temperature. For this reason, when a set level of a determination threshold value is excessively high, a small short defect cannot be detected. In contrast, when the set level of the determination threshold value is excessively low, the probability of erroneous determination is increased to unexpectedly determine even an inherently acceptable product to be defective. This leads to problems in measurement accuracy.
FIG. 3 shows a memory array configuration for describing a leaky-row measurement method that is employed to reduce testing time. According to the measurement method, row lines are alternately selected to be unselected row lines or selected row lines, whereby a plurality of row lines are selected in one time to undergo the measurement. However, pass-through current, as described above, occurs in a plurality of row drivers corresponding to selected row lines, so that the pass-through current is significantly increased. This results in further deterioration in the measurement accuracy, therefore making it very difficult to reduce the testing time while maintaining measurement accuracy.
Another conventional related art is disclosed in Japanese Unexamined Patent Application Publication No. 7-192500, for example. The publication discloses a measurement method in which, when testing row lines arranged parallel to one another, the row lines are held in a floating state and are alternately set to a reference potential; and remaining other row lines are applied with a testing voltage; thereby the testing time is reduced. Even in the method, however, problems similar to those with the conventional related art described above are pending resolution for row drivers designed in consideration of high-speed accessibility.
Recently, in the field of nonvolatile semiconductor storage devices, in line with advancement in miniaturization technology, defects occurring in the stage of semiconductor manufacture are even more required to be eliminated. Concurrently, reduction in the testing time is even more required to meet requirements for one-time mass production. However, according to conventional techniques as described above, measurement errors during the measurement are increased, so that problems still remains unsolved in that defective products cannot be appropriately identified. Further, sufficient reduction in the testing time is cannot be implemented.